1. Field of the Invention
The present invention relates to an electrically erasable and reprogrammable nonvolatile semiconductor memory (EEPROM). More particularly, the invention relates to a memory having a system for simultaneously erasing a plurality of cell blocks.
2. Description of the Related Art
In an EEPROM (electrically erasable and reprogrammable nonvolatile memory) using a stacked gate type MOS transistor of a structure in which a floating gate and a control gate are stacked, there have been known, as systems for erasing data in a memory cell, a chip erasing system in which data in all memory cells on a memory chip are flashed, i.e., simultaneously erased and an individual block erasing system in which a memory cell array is divided into a plurality of cell blocks and data in the cells in the cell blocks are flashed, i.e., simultaneously erased by block units. There has also been disclosed a plural block simultaneous erasing system in which data in a selected cell blocks are flushed, i.e., simultaneously erased so as to make an erasing period shorter than the individual block erasing system (Japanese Patent Application No. 4-281193 relating to a co-pending application filed by the present applicant).
In an EEPROM having such an individual block erasing system or a plural block erasing system, selection/nonselection is performed for each block so as enable reading, writing and erasing data therein.
FIG. 10 is a view showing a part of a first preferred embodiment of EEPROM disclosed in Japanese Patent Application No. 4-281193. The disclosed EEPROM has a plural block erasing system.
In the drawing, 11.sub.1 to 11n are a plurality of cell blocks each having an array of a plurality of nonvolatile memory cells, in which data in selected cell blocks are simultaneously erased by applying erasing voltages to control gates of the memory cells of the selected cell blocks. 12.sub.1 to 12n are a plurality of address data hold circuits provided corresponding to the plurality of cell blocks 11.sub.1 to 11n to hold select data indicating selection of the corresponding cell blocks. 13.sub.1 to 13n are a plurality of row subdecoders provided corresponding to the plurality of cell blocks 11.sub.1 to 11n. These row subdecoders select and erase all the memory cells of the corresponding cell blocks 11.sub.1 to 11n if the select data are held in the corresponding select data hold circuits by applying erasing voltages to the control gates thereof.
An address register 14 holds a block address signal specifying one of block addresses (0 to 255) of the plurality of cell blocks 11.sub.1 to 11n.
A row predecoder 15 decodes a block address signal input from the address register 14 or an address buffer (not shown). The row predecoder 15 functions as a select data input circuit to input a select data selecting a specified cell block to a select data hold circuit corresponding to the specified cell block. In the simultaneous erasing of data in the plurality of blocks, the predecoder 15 inputs, by responding to a plurality of block addresses specifying a plurality of cell blocks from which data are to be erased, select data to the select data hold circuits corresponding to the specified plurality of cell blocks from which data are to be erased.
A select data read circuit 16 reads select data held in the plurality of select data hold circuits 12.sub.1 to 12n. A command register 17 holds a command signal input via an I/O buffer 18. A verify control circuit 19 controls, upon receiving the command signal from the command register 17, a cell data reading operation performed so as to check (hereinafter called verify reading operation) whether cell data have been sufficiently erased from the target blocks or not, based on the select data read from the select data read circuit 16. The verify control circuit 19 also controls a content (block addresses) of the address register 14 while performing the verify reading operation.
A memory chip having such a plural block erasing system is usually used in a manner that a plurality of such chips are assembled in a memory and incorporated in a computer system, etc. In order to secure reliability of data, redundancy chips are generally provided in such a system.
In the memory chip, by means of a sequencer circuit (not shown), a series of operations from erasing to verify reading after erasing are controlled with respect to a plurality of simultaneous erasing blocks specified to be erased by the system side. When it is determined that requirements for erasing are not satisfied, an erase error signal (fail end signal indicating failure of an erasing operation) indicating erasing failure is output to the outside of the chip. In this case, a system for repeating controlling of a series of operations from erasing to verify reading by a specified number of times until the requirements for erasing are met may be utilized. By means of this system, when it is determined that the requirements are not satisfied even by repeating controlling of the operations by the specified number of times, an erase error signal, that is, a fail end signal, is output to the outside of the chip.
When the erase operation is in failure, it is required for the system side to replace the erase failure block with a cell block of a redundancy chip. To achieve this requirement, operations are carried out in the system side to detect the address of the erase failure block, convert the detected address to an address in the redundancy chip and store the converted address. When an erase operation is carried out to specified cell blocks in a memory chip having the plural block simultaneous erasing system, thereafter an erase failure block exists in the specified cell blocks and thus the erase operation is ended in failure, then the system side is required to carry out a verify reading operation to all of the addresses of the specified cell blocks to determine the address of the erase failure block.
In the memory chip having a plural block erasing system presented in the Unexamined Patent Publication No. 4-281193, it is impossible to directly output addresses of erase failure blocks to the outside of the chip. Therefore, even when erase failure exists only in portions of the plurality of erasing target blocks (the requirements for erasing have not been satisfied) while erasing can be normally performed for the remaining blocks (the requirements for erasing have been met), in order to detect addresses of the erase failure blocks, upon receiving a fail end signal the system side must perform verify reading again for all the plurality of erasing target blocks. This means that verify reading is unnecessarily repeated for the blocks for which the erasing operations have been normal, and thus the operation time of the whole system is lengthened. To replace the erase failure block, the system side should have two functions, i.e., an address hold function and a verify function. The address hold function is to hold the addresses of the specified cell blocks to be erased until a pass signal is outputted for the erase operation, and the verify operation is to successively input addresses to all of the specified cell blocks to read data therefrom for verify. This complicates the structure of the system.
In this memory device, it is the precondition that the operations from the verify-read through the determination of pass/fail are automatically controlled in the write mode and the erase mode. When the erase operation is carried out, the system issues an erase command and addresses for specifying cell blocks to be erased to monitor an R/B (read/busy) signal to determine the end of the erase operation. The R/B signal can be monitored on R/B output terminal of the memory chip or the I/O terminal in the status read mode. After the erase operation end is detected, a P/F (pass/fail) information is checked while maintaining the status read mode. All the operation regarding the data erase is completed, when the erase operation is correctly performed. However, since erase failure will occur, though the probability is so low as one per millions, the system side is required to have the verify function and the P/F determination function. If probability of erase failure occurrence is zero, the verify function and the P/F determination function in the system side is not necessary.
As described above, in the EEPROM employing the plural block simultaneous erasing system presented in the Unexamined Patent Publication No. 4-281193, a problem has been that since the system side detects the addresses of the erase failure blocks even when erase failure exists only in portions of the plurality of cell blocks, verify reading is unnecessarily repeated for the blocks from which the data have been normally erased.